The present invention relates to a semiconductor device and an IO-cell. In particular, the present invention relates to a semiconductor device including IO-cells arranged along the periphery of a semiconductor chip, and its IO-cells.
A semiconductor integrated circuit (also referred to as “LSI: Large Scale Integration”) needs to be equipped with power supply lines in order to supply electric power to transistors formed on a semiconductor substrate. Large electric currents flow though these power supply lines. Therefore, it is necessary to avoid problems that would otherwise occur in the lines due to these large currents such as a voltage drop (IRDrop) and electro-migration in order to improve the performance and/or the reliability of the LSI. Therefore, Japanese Patent No. 4275110 and Japanese Unexamined Patent Application Publications No. H04-116850 and No. 2010-219332 disclose examples of methods of wiring power supply lines.
In particular, Japanese Patent No. 4275110 discloses an example in which two power supply lines are formed in a comb-like pattern, and the two power supply lines are arranged so that their comb-like sections engage with each other and a semiconductor chip is covered with these two power supply lines. Japanese Unexamined Patent Application Publications No. H04-116850 discloses an example in which power supply lines are arranged in a ring shape along the periphery of a chip. Japanese Unexamined Patent Application Publications No. 2010-219332 discloses an example of a semiconductor device including surrounding power supply lines in which power supply lines supplied with a power supply voltage and ground lines supplied with a ground voltage are alternately arranged, and in which surrounding power supply lines having the same potential are connected to each other through lines perpendicular to the extending direction of the surrounding lines.